This invention relates to a semiconductor memory device which can store a character pattern in desired memory locations, and which can be used as, for example, an image memory.
There has been known a semiconductor memory device which stores words each made up of a predetermined number of bits, one by one. As shown in FIG. 1, this type of semiconductor memory device comprises address latch circuit 12, row decoder circuit 13, column decoder and sense amplifier 15, and memory 17. Address latch circuit 12 latches address signals A.sub.0 to Am-1 on address bus 11. Row decoder circuit 13 decodes address signals Ap to Am-1 supplied from address latch circuit 12 via address bus 14. Column decoder and sense amplifier 15 decodes address signals A.sub.0 to Ap-1 supplied from address latch circuit 12 via address bus 16. Memory cells of memory 17 are selectively designated by row decoder circuit 13 and column decoder and sense amplifier 15. N-bit data from memory 17 is supplied to output buffer 19 via 2.sup.p .times.n-bit line 18 and column decoder and sense amplifier 15. Output buffer 19 is controlled by control circuit 20 in accordance with a control signal on control input line 21, which is supplied from an external control circuit (not shown), and outputs n-bit data supplied via column decoder and sense amplifier 15 to data output line 22.
If an m-bit address signal is used for designating one word of n bits, memory 17 contains a matrix memory cell array of 2.sup.q rows.times.(2.sup.p .times.n) columns (p+q=m). In this case, one row in memory 17 is selected by address signals A.sub.p to A.sub.m-1. Then, from a plurality of words in the selected row, one word is selected by address signals A.sub.0 to A.sub.p-1. In this way, data is accessed, word by word, in the word area. The n bits of one word are fixed in their locations, and are accessed simultaneously.
In the semiconductor memory device used as an image memory, there are cases where image data is stored in two word areas as shown by hatched lines in FIG. 2, without any restriction by the boundary between the word areas. In such cases, an access request for the n-bit data stored in two adjacent word areas is needed. As shown in FIG. 2, a plurality of word areas WAll to WAMN each having 0-th to (n-1)th bit areas BAl to BAn are allotted in memory 17. For example, word area WAll is allotted to address location X. Word areas WA12, WAIN, WA21 and WA31 are respectively allotted to address locations (X+1), (X+Y-1), (X+Y) and (X+2Y). Memory area MA which stores n-bit image data ID, includes successive "n" bit areas extending to word area WA32 at address location (X+2Y+1) and word area WA33 at address location (X+2Y+2).
In the memory device shown in FIG. 1, in reading out n-bit image data ID stored in memory area MA, memory area MA cannot be directly accessed. Some steps are needed for reading out such data. First, word areas WA32 and WA33 are accessed to read out the 2n-bit data. Then either by processing the readout 2n-bit data in an external circuit, or by processing the 2n-bit data by software, the n-bit image data is extracted. As described above, conventionally, it is possible to make a direct access to one-word data in a word area, but it is impossible to make a direct access to one-word data stored in the word areas containing a bit boundary for separating them. This leads to the decrease of data processing speed.